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1·PLS algorithm is presented as a new logic synthesis algorithm for PAL.

本文针对pal器件的分析提出一种新型逻辑综合算法，即pls算法。

2·The design includes system level design, RTL level design and logic synthesis.

设计工作包括系统级设计、RTL级设计、逻辑综合。

3·Sequential logic synthesis is an important part of RTL synthesis system design.

时序逻辑综合是RTL综合系统设计中的一个重要部分。

4·Now the success of, the commercial success of logic synthesis is probably due to two factors.

现在的成功，在商业上的成功逻辑综合可能是由于两个因素造成的。

5·We are present a heuristic algorithm of logic synthesis fitted to large number of input variable.

本文给出了适用于大数目输入变量的逻辑综合启发式算法。

6·Optimization in automatic logic synthesis is usually done after the Boolean equations are set up.

逻辑自动综合中控制部分的优化一般是在布尔方程确定之后进行。

7·In theory, a logic synthesis tool guarantees that the first netlist is logically equivalent to the RTL source code.

在理论上，逻辑综合工具，保证第一网表是合乎逻辑相当于RTL源代码。

8·In the area of logic synthesis, a procedure of derivation of complements for a given product set is frequently used.

在逻辑综合的领域内，经常使用求给定积项集合补集的过程。

9·The significance, motivation, progress, and challenges was analyzed for reversible logic synthesis of quantum circuit.

本文阐述的重点是量子电路的可逆逻辑综合问题。

10·Verification and logic synthesis result show that the DDC chip can meet the requirement, also have stable performance.

验证和逻辑综合结果表明DDC芯片能满足设计要求，性能稳定。