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1·Phase locked loop technique offers a way to resolve this problem.

锁相式频率合成技术提供了解决这一问题的思路。

2·It also give an improved method for PLL (phase locked loop) to extract coherent carrier.

本文还对相干载波提取中的锁相环提出了一种改进方法。

3·The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.

定量分析了数字式锁相倍频器输出信号的相位抖动。

4·An automatic accurate synchronization control scheme which adopts phase locked loop principle is presented.

利用锁相环路原理提出锁相自动准同期控制方案。

5·Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).

本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。

6·A novel all-digital phase locked loop (PLL), applied to the carrier synchronization of communication systems, is designed.

设计了一种用于通信系统载波同步的新数字锁相环。

7·Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).

然后介绍了锁相环(PLL)的基本结构、相位模型、频率响应、噪声及杂散性能。

8·In the process of signal digital intermediate-frequency received, digital down convertion, frequency tracking of carrier and phase locked loop are the keys.

在信号的中频数字接收过程中，数字下变频、载波频率与相位跟踪是设计的关键所在。

9·The basic principle of phase locked loop (PLL) has been introduced, and the transmission function of the phase noises of every part of PLL has been analyzed.

介绍了锁相环的基本原理，分析了锁相环各部分电路相位噪声的传递函数。

10·High precise measuring and tracking of carrier frequency-deviation is necessary to the realization of a high performance phase locked loop in carrier recovery.

载波恢复中高精度的频偏检测与跟踪是高性能锁相位环路实现的必要条件。