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1·This wafer level chip size package (WL-CSP) process encases the die in a solid die-size glass shell.

圆片级芯片尺寸封装（WL-CSP）工艺是在固态芯片尺寸玻璃外壳中装入芯片。

2·Semiconductor device, semiconductor wafer, chip size package, and methods of manufacturing and inspection therefor.

半导体器件，半导体晶片，芯片尺寸封装及制作和检测方法。

3·The emphasis on minimizing cost, complexity and chip size is permeating all aspects of the standardization process.

在此标准化过程的方方面面都贯穿着对降低成本、复杂度和芯片尺寸的强调。

4·The new Samsung UFS memory satisfies needs for ultra-fast speed, large data capacity and compact chip size in high-end smart phones.

新的三星内存ufs满足需求的超速度快，容量大，结构紧凑芯片尺寸的中高端智能手机。

5·Due in part to the smaller chip size, the new IRED is a lower-cost alternative to Osram's SFH 4715A for systems with mid-range output requirements.

部分原因是由于在更小的芯片尺寸，新IRED是一种低成本的替代欧司朗的SFH 4715A用于中档输出要求的系统。

6·Therefore, the metal oxide semiconductor can be used efficiently without additional manufacturing of a capacitor, and can save the chip size so as to reduce the cost.

如此可有效率地利用该金属 氧化物半导体，并无须另外制作电容，可节省该芯片的尺寸大小，进而降低 成本。

7·The maximum stress of PBGA121 soldered joints increases when chip size increases, while the maximum stress of PBGA81 soldered joints decreases first and then increases.

芯片尺寸改变时，PB - GA121焊点的最大应力值随芯片尺寸的增大而增大，但PBGA81的最大应力值随芯片尺寸增大先减小后增大。

8·The expected productivity increase by shrinking the chip size combined with the use of 300mm wafers is the basis for a significant reduction of production cost per chip.

减小缩小芯片大小尺寸和使用300mm晶圆将实现的生产率力增长提高是内存产品芯片生产成本大幅度下降的关键基础。

9·To reduce the power dissipation and chip size of digital calibration circuits of pipelined analog-to-digital converter (ADC), a new statistics-based background calibration technique is presented.

为了降低流水线模数转换器中数字校准电路的规模和功耗，提出了一种新的基于信号统计规律的后台数字校准技术。

10·In this design, a 2-level round-robin arbitration algorithm is chosen to improve system performance, and state machine coding style is also optimized to reduce chip size and dynamic power consumption.

设计中选择了两优先级轮转仲裁算法，以提高系统性能；优化了状态机编码方式，以减小芯片面积和降低动态功耗。